FIG. 1 illustrates a conventional dynamic NAND gate 11 wherein the complementary outputs B and B' are precharged to logic 1 on the falling edge of a precharge dock PCLK and wherein, on the rising edge of PCLK, one of the complementary outputs remains at logic 1 and the other begins to fall to logic 0, depending on the logic state of logic inputs A1, A2, A1' and A2'. Such precharged, complementary outputs are produced in dynamic circuitry like dual-rail domino circuitry, and are also produced by the sense amplifiers of conventional memory circuitry such as SRAM circuitry. When interfacing between dynamic output signals such as shown in FIG. 1 and static circuitry which requires a static logic signal input, it is desirable to provide an interface which is both fast and energy-efficient.
FIG. 2 illustrates a conventional interface 21 which converts precharged dynamic signals such as B and B' into a static logic signal Q.sub.out which is then applied to an input of a static circuit. FIG. 3 illustrates the truth table for the latch circuit 23 of FIG. 2, which latch circuit 23 includes NAND gates 25 and 27. The possible logic states of signals B and B' are shown on the left side of the FIG. 3 truth table, and the corresponding logic states of signals Q and Q' are shown on the right side of the FIG. 3 truth table. When the logic state of signals B and B' changes from 0 and 1, respectively, through the precharged state of 1 and 1, to the logic state of 1 and 0, respectively, the final transition of B' from 1 to 0 must propagate through 3 logic gates, namely NAND gate 27, NAND gate 25 and inverter 29, before Q.sub.out transitions from 0 to 1 as desired. When the logic state of signals B and B' transitions from 1 and 0, respectively, through the precharged state of 1 and 1, to the logic state of 0 and 1, respectively, the final transition of B from 1 to 0 must propagate through 2 logic gates, namely NAND gate 25 and inverter 29 before Q.sub.out transitions from 1 to 0 as desired.
The gate length of all transistors described herein is 0.6 micron unless otherwise stated.
The conventional NAND gate transistor design of FIG. 4 is typically used for NAND gates 25 and 27 of FIG. 2. The inputs 31 and 33 of NAND gate 25, and the output 35 of NAND gate 25 are designated in the transistor diagram of FIG. 4. Assuming that: the n-channel transistors of NAND gates 25 and 27 have a 9 micron gate width and the p-channel transistors of NAND gates 25 and 27 have a 19 micron gate width; the n-channel transistor of inverter 29 has a 21 micron gate width and the p-channel transistor of inverter 29 has a 34.5 micron gate width; and a 0.3 pf load is connected to Q.sub.out ; the average propagation delay through interface 21 (sometimes through 3 logic gates and sometimes through 2 logic gates as discussed above) is 411 ps. The stacked arrangement of the n-channel transistors of FIG. 4 requires these transistors to have a relatively wide gate width of 9 microns in order to achieve the aforementioned average propagation delay. However, the relatively large n-channel transistors add more input capacitance, disadvantageously resulting in a relatively high average power dissipation of 0.428 mW.
The present invention provides interface circuitry which converts a precharged dynamic logic signal to a static logic signal with a lower average propagation delay and a lower average power dissipation than the prior art arrangement.